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CAT22C10
256-Bit Nonvolatile CMOS Static RAM
FEATURES
s Single 5V Supply s Fast RAM Access Times: s Low CMOS Power Consumption:
-200ns -300ns
s Infinite EEPROM to RAM Recall s CMOS and TTL Compatible I/O s Power Up/Down Protection s 100,000 Program/Erase Cycles (E2PROM)
-Active: 40mA Max. -Standby: 30A Max.
s JEDEC Standard Pinouts:
-18-lead DIP -16-lead SOIC
s 10 Year Data Retention s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT22C10 NVRAM is a 256-bit nonvolatile memory organized as 64 words x 4 bits. The high speed Static RAM array is bit for bit backed up by a nonvolatile EEPROM array which allows for easy transfer of data from RAM array to EEPROM (STORE) and from EEPROM to RAM (RECALL). STORE operations are completed in 10ms max. and RECALL operations typically within 1.5s. The CAT22C10 features unlimited RAM write operations either through external RAM writes or internal recalls from EEPROM. Internal false store protection circuitry prohibits STORE operations when VCC is less than 3.0V. The CAT22C10 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles (EEPROM) and has a data retention of 10 years. The device is available in JEDEC approved 18-lead plastic DIP and 16-lead SOIC packages.
PIN CONFIGURATION
DIP Package (L) SOIC Package (W)
A4 A3 A2 A1 A0 CS Vss STORE
PIN FUNCTIONS
Pin Name A0-A5 Function Address Data In/Out Write Enable Chip Select Recall Store +5V Ground No Connect
NC A4 A3 A2 A1 A0 CS Vss STORE
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
Vcc NC A5 I/O3 I/O2 I/O1 I/O0 WE RECALL
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Vcc A5 I/O4 I/O3 I/O2 I/O1 WE RECALL
I/O0-I/O3 WE CS RECALL STORE VCC VSS NC
(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
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Doc. No. MD-1082, Rev. R
CAT22C10
BLOCK DIAGRAM
EEPROM ARRAY
A0 A1 A2 A3 A4 A5 STORE RECALL
ROW
STATIC RAM
STORE
SELECT
ARRAY
RECALL
COLUMN SELECT
CONTROL LOGIC
READ/WRITE CIRCUITS
CS
WE
I/O0 I/O1 I/O2 I/O3
MODE SELECTION(1)(2)(3) Input Mode Standby RAM Read RAM Write (EEPROMRAM) (EEPROMRAM) (RAMEEPROM) (RAMEEPROM) POWER-UP TIMING(4) Symbol VCCSR Parameter VCC Slew Rate Min. 0.5 Max. 0.005 Units V/ms CS H L L X H X H WE X H L H X H X RECALL H H H L L H H STORE H H H H H L L I/O Output High-Z Output Data Input Data Output High-Z RECALL Output High-Z RECALL Output High-Z STORE Output High-Z STORE
Note: (1) RECALL signal has priority over STORE signal when both are applied at the same time. (2) STORE is inhibited when RECALL is active. (3) The store operation is inhibited when VCC is below 3.0V. (4) This parameter is tested initially and after a design or process change that affects the parameter.
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
CAT22C10
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(2) .............. -2.0 to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 100,000 10 2000 100 Max.
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Units Cycles/Byte Years Volts mA
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS VCC = +5V 10%, unless otherwise specified. Limits Symbol ICC Parameter Current Consumption (Operating) Current Consumption (Standby) Input Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage RAM Data Holding Voltage 1.5 2 0 2.4 0.4 5.5 Min. Typ. Max. 40 Unit mA Conditions All Inputs = 5.5V TA = 0C All I/O's Open CS = VCC All I/O's Open 0 VIN 5.5V 0 VOUT 5.5V
ISB ILI ILO VIH VIL VOH VOL VDH
30 10 10 VCC 0.8
A A A V V V V V
IOH = -2mA IOL = 4.2mA VCC
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN(1) Parameter Input/Output Capacitance Input Capacitance Max. 10 6 Unit pF pF Conditions VI/O = 0V VIN = 0V
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
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Doc No. MD-1082, Rev. R
CAT22C10
A.C. CHARACTERISTICS, Write Cycle VCC = +5V 10%, unless otherwise specified. 22C10-20 Symbol tWC tCW tAS tWP tWR tDW tDH tWZ(1) tOW Parameter Write Cycle Time CS Write Pulse Width Address Setup Time Write Pulse Width Write Recovery Time Data Valid Time Data Hold Time Output Disable Time Output Enable Time 0 Min. 200 150 50 150 25 100 0 100 0 Max. 22C10-30 Min. 300 150 50 150 25 100 0 100 Max. Unit ns ns ns ns ns ns ns ns ns CL = 100pF +1TTL gate VOH = 2.2V VOL = 0.65V VIH = 2.2V VIL = 0.65V Conditions
A.C. CHARACTERISTICS, Read Cycle VCC = +5V 10%, unless otherwise specified. 22C10-20 Symbol tRC tAA tCO tOH tLZ(1) tHZ(1) Parameter Read Cycle Time Address Access Time CS Access Time Output Data Hold Time CS Enable Time CS Disable Time 0 0 100 Min. 200 200 200 0 0 100 Max. 22C10-30 Min. 300 300 300 Max. Unit ns ns ns ns ns ns Conditions CL = 100pF +1TTL gate VOH = 2.2V VOL = 0.65V VIH = 2.2V VIL = 0.65V
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
CAT22C10
A.C. CHARACTERISTICS, Store Cycle VCC = +5V 10%, unless otherwise specified. Limits Symbol tSTC tSTP tSTZ(1) tOST(1) Parameter Store Time Store Pulse Width Store Disable Time Store Enable Time 0 200 100 Min. Max. 10 Units ms ns ns ns CL = 100pF + 1TTL gate VOH = 2.2V, VOL = 0.65V VIH = 2.2V, VIL = 0.65V Conditions
A.C. CHARACTERISTICS, Recall Cycle VCC = +5V 10%, unless otherwise specified. Limits Symbol tRCC tRCP tRCZ tORC tARC Parameter Recall Cycle Time Recall Pulse Width Recall Disable Time Recall Enable Time Recall Data Access Time 0 1.1 Min. 1.4 300 100 Max. Units s ns ns ns s CL = 100pF + 1TTL gate VOH = 2.2V, VOL = 0.65V VIH = 2.2V, VIL = 0.65V Conditions
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
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Doc No. MD-1082, Rev. R
CAT22C10
DEVICE OPERATION
The configuration of the CAT22C10 allows a common address bus to be directly connected to the address inputs. Additionally, the Input/Output (I/O) pins can be directly connected to a common I/O bus if the bus has less than 1 TTL load and 100pF capacitance. If not, the I/O path should be buffered. When the chip select (CS) pin goes low, the device is activated. When CS is forced high, the device goes into the standby mode and consumes very little current. With the nonvolatile functions inhibited, the device operates like a Static RAM. The Write Enable (WE) pin selects a write operation when WE is low and a read operation when WE is high. In either of these modes, an array byte (4 bits) can be addressed uniquely by using the address lines (A0-A5), and that byte will be read or written to through the Input/Output pins (I/O0-I/O3). The nonvolatile functions are inhibited by holding the STORE input and the RECALL input high. When the RECALL input is taken low, it initiates a recall operation which transfers the contents of the entire EEPROM
array into the Static RAM. When the STORE input is taken low, it initiates a store operation which transfers the entire Static RAM array contents into the EEPROM array. Standby Mode The chip select (CS) input controls all of the functions of the CAT22C10. When a high level is supplied to the CS pin, the device goes into the standby mode where the outputs are put into a high impendance state and the power consumption is drastically reduced. With ISB less than 100A in standby mode, the designer has the flexibility to use this part in battery operated systems. Read When the chip is enabled (CS = low), the nonvolatile functions are inhibited (STORE = high and RECALL = high). With the Write Enable (WE) pin held high, the data in the Static RAM array may be accessed by selecting an address with input pins A0-A5. This will occur when the outputs are connected to a bus which is loaded by no more than 100pF and 1 TTL gate. If the loading is greater than this, some additional buffering circuitry is recommended.
Figure 1. Read Cycle Timing
tRC ADDRESS tAA CS tLZ DATA I/O tOH DATA VALID tHZ HIGH-Z tCO
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
CAT22C10
Write With the chip enabled and the nonvolatile functions inhibited, the Write Enable (WE) pin will select the write mode when driven to a low level. In this mode, the address must be supplied for the byte being written. After the set-up time (tAS), the input data must be supplied to pins I/O0-I/O3. When these conditions, including the write pulse width time (tWP) are met, the data will be written to the specified location in the Static RAM. A write function may also be initiated from the standby mode by driving WE low, inhibiting the nonvolatile functions, supplying valid addresses, and then taking CS low and supplying input data.
Figure 2. Write Cycle Timing
tWC ADDRESS tCW CS tAS WE tDW DATA IN tWZ DATA OUT HIGH-Z DATA VALID tOW tDH tWP tWR
Figure 3. Early Write Cycle Timing
tWC ADDRESS tCW CS tAS tWP WE tDW DATA IN DATA VALID tDH tWR
DATA OUT
HIGH-Z
(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
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Doc No. MD-1082, Rev. R
CAT22C10
Recall At anytime, except during a store operation, taking the RECALL pin low will initiate a recall operation. This is independent of the state of CS, WE, or A0-A5. After the RECALL pin has been held low for the duration of the Recall Pulse Width (tRCP), the recall will continue independent of any other inputs. During the recall, the entire contents of the EEPROM array is transferred to the Static RAM array. The first byte of data may be externally accessed after the recalled data access time from end of recall (tARC) is met. After this, any other byte may be accessed by using the normal read mode. If the RECALL pin is held low for the entire Recall Cycle time (tRCC), the contents of the Static RAM may be immediately accessed by using the normal read mode. A recall operation can be performed an unlimited number of times without affecting the integrity of the data. The outputs I/O0-I/O3 will go into the high impedance state as long as the RECALL signal is held low. Store At any time, except during a recall operation, taking the STORE pin low will initiate a store operation. This takes Figure 4. Recall Cycle Timing
place independent of the state of CS, WE or A0-A5. The STORE pin must be held low for the duration of the Store Pulse Width (tSTP) to ensure that a store operation is initiated. Once initiated, the STORE pin becomes a "Don't Care", and the store operation will complete its transfer of the entire contents of the Static RAM array into the EEPROM array within the Store Cycle time (tSTC). If a store operation is initiated during a write cycle, the contents of the addressed Static RAM byte and its corresponding byte in the EEPROM array will be unknown. During the store operation, the outputs are in a high impedance state. A minimum of 100,000 store operations can be performed reliably and the data written into the EEPROM array has a minimum data retention time of 10 years. DATA PROTECTION DURING POWER-UP AND POWER-DOWN The CAT22C10 has on-chip circuitry which will prevent a store operation from occurring when VCC falls below 3.0V typ. This function eliminates the potential hazard of spurious signals initiating a store operation when the system power is below 3.0V typ.
tRCC ADDRESS tRCP RECALL tARC CS tORC HIGH-Z DATA I/O tRCZ DATA UNDEFINED DATA VALID
Figure 5. Store Cycle Timing
tSTC tSTP STORE tSTZ DATA I/O HIGH-Z
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
CAT22C10
EXAMPLE OF ORDERING INFORMATION(1)
Prefix CAT
Device # 22C10
Suffix W I - 20 - T1
Company ID
Product Number 22C10
Temperature Range I = Industrial (-40C to +85C) E = Extended (-40C to +125C)(3)
T: Tape & Reel 1: 1,000/Reel
Package L: PDIP W: SOIC, JEDEC
Speed 20: 200ns 30: 300ns
ORDERING INFORMATION
Orderable Part Numbers (for Pb-Free Devices) CAT22C10LE20 CAT22C10LE30 CAT22C10LI20 CAT22C10LI30 CAT22C10WE-20-T1 CAT22C10WE-30-T1 CAT22C10WI-20-T1 CAT22C10WI-30-T1
Notes: (1) The device used in the above example is a CAT22C10WI-20-T1 (SOIC, Industrial Temperature, 200ns, Tape & Reel, 1,000/Reel). (2) For additional package option please contact your nearest Catalyst Semiconductor Sales office. (3) Extended Temperature available upon request.
(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.
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Doc No. MD-1082, Rev. R
CAT22C10
REVISION HISTORY
Date 16-Apr-04 Revision Description O Add Lead free logo Update Features Update Pin Configuration Update Ordering Information Update Revision Number Update Example of Ordering Information Change logo and fine print to ON Semiconductor Update Example of Ordering Information Update Ordering Information table
24-Jun-08 17-Mar-09 31-Jul-09
P Q R
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability a r i s i n g out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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(c) 2009 SCILLC. All rights reserved. Characteristics subject to change without notice.

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